1. Field of the Invention
The present invention relates to a non-volatile memory device whereby the time required for initialization can be reduced.
2. Background Information
The flash memory described in JP-3392839-B, for example, and particularly NAND-type flash memory, is structured so that writing and reading is performed in page units (between 512 bytes and 2048 bytes). FIGS. 16 and 17 show the structure of the NAND-type flash memory device 100, described in JP-3392839-B. The NAND-type flash memory device 100 comprises a non-volatile memory array 115, a sense amp 190, a data buffer 200, a column address buffer/decoder 210, a row address buffer/decoder 220, and a controller 300.
Within the non-volatile memory array 115, a plurality of non-volatile memory cells 170 are disposed at the intersections of word lines 129 and bit lines 139 that cross each other as shown in FIG. 17. Furthermore, the non-volatile memory array 115 includes a plurality of blocks 110, which are data erase units, the blocks 110 including a plurality of pages 120, which are data read and write units. Furthermore, each page 120 includes a first region 150 and a second region 160. Data that is read out to the exterior of the flash memory device 100, and data that is written from the exterior of the flash memory device 100, is stored in the first region 150. Meanwhile, data that is associated with the data of the first region 150 is stored in the second region 160.
The controller 300 accepts, from the exterior of the flash memory device 100, a variety of commands and addresses for accessing the non-volatile memory array 115. The row address buffer/decoder 220 selects the appropriate word line 129 based on the row address that has been input, and the column address buffer/decoder 210 selects the appropriate bit line 139 based on the column address that has been input. Here, reading data from, or writing data to, the non-volatile memory array 115 is done in page units. When writing, the data buffer 200 temporarily stores, in page units, the data that has been input from the exterior of the flash memory device 100, and writes this to the non-volatile memory cells in page units. Meanwhile, when reading, the data buffer 200 temporarily stores the data that has been read out, in page units, via the sense amp 190, and outputs the data to the exterior of the flash memory device 100.
FIG. 18 is a timing chart for reading out data from the flash memory device 100. The READ command for reading out data is input to the controller 300 along with the external signal CLE. Following this, when the addresses ADDR00-ADDR0n of the data to be read are input to the controller 300 along with the external signal ALE, the data from the non-volatile memory cells in the corresponding page 120 is stored in the data buffer 200 via the sense amp 190. The data that is stored in the data buffer 200 is read out when the external command NRE is changed after the R/B signal transitions from low to high.
When writing to the non-volatile memory array 115, in order to avoid defective blocks and blocks to which data has already been written, data must be written to blocks that have been erased. Thus, information for associating the data that has been written to the blocks with the logical addresses of that data, and information regarding defective blocks, is written to the second region 160. Furthermore, the data that is read out from the second region 160 is stored in the volatile memory cells of a RAM (Random Access Memory) or the like; thus the data is lost when the power supply is turned off. This requires that data be read out from the second region 160 each time initialization is performed when the power supply is turned on. Consequently, in the flash memory device 100, each time the power supply is turned on, there is a need to perform the initialization process, by reading out the data from the second region 160 so as to know the relationship between the aforementioned data and addresses and so as to know the locations of the defective blocks.
In the flash memory device 100, first the non-volatile memory array 115 is accessed in order to read out the data in the second region 160 in page units during the initialization process. FIG. 19 shows the data structure for the data that is read out to the data buffer 200 in page units. As is shown in FIG. 19, the data that is read out to the data buffer 200 comprises the data of the first region 150 and the second region 160. The memory control unit on the exterior of the flash memory device 100 generates and stores an address conversion table for defining, for example, associations between the data and the addresses in the data that has been read out, based on the data from the second region.
In the initialization process, the second region 160 of the first page 120 in each of the blocks 110, for example, is read out. The non-volatile memory capacity of the flash memory device 100 is 64 Mb, the page comprises a first region of 512 bytes and a second region of 16 bytes, one block comprises 32 pages and the time required to read one page is 25 μs (block size is 16 Kbytes and bock number is 512), so approximately 13 μs is required to read out the data in the second region 160. If the non-volatile memory capacity is larger, at 8 Gb, the page comprises a first region of 2048 bytes and a second region of 64 bytes, with one block comprising 64 pages (block size is 128 Kbytes and bock number is 8192). If the time required to read a single page is 25 μs, then it would take approximately 230 ms to read out the data in the second region 160.
The time required for the initialization process increases with the non-volatile memory capacity of the flash memory device 100, increasing the time before it is possible to read or write the data in the non-volatile memory array 115 correctly.
Thus, an object of the present invention is to provide a non-volatile memory device that can reduce the time required for the initialization process. This invention addresses this object as well as other objects, which will become apparent to those skilled in the art from this disclosure.